Phase-change materials are capable of being electrically programmed between a first structural state where the material is generally amorphous and a second structural state where the material is generally crystalline. The term “amorphous”, as used herein, refers to a structural condition which is relatively less ordered or more disordered than a single crystal. The term “crystalline”, as used herein, refers to a structural condition which is relatively more ordered than amorphous. The phase-change material exhibits different electrical characteristics depending upon its state. For instance, in its crystalline, more ordered state the material exhibits a lower electrical resistivity than in its amorphous, less ordered state. Each material phase can be conventionally associated with a corresponding logic value. For example, the lower resistance crystalline state may be associated with a set state and a logic “1” while the higher resistance amorphous state may be associated with a reset state and a logic “0”.
Materials that may be used as a phase-change material include, without limitation, alloys of the elements from group VI of the Periodic Table. These group VI elements are referred to as the chalcogen elements and include the elements Te and Se. Alloys that include one or more of the chalcogen elements are referred to as chalcogenide alloys. An example of a chalcogenide alloy useful as a phase-change memory material is the alloy Ge2Sb2Te5 (also referred to as GST225).
Hence, certain chalcogenide materials are phase-change materials that may be electrically programmed to undergo structural change. As will be discussed in more detail below, there are other chalcogenide materials that may not readily undergo such structural changes and may remain in a relatively amorphous state. Such materials may be useful as threshold switching materials which become highly conductive (without substantial change of structure) by application of a sufficiently high voltage. A volume of phase-change material can be reversibly programmed between a high resistance state referred to as a reset state and a low resistance state referred to as a set state to provide a binary mode of operation. A volume of phase-change material may also be programmed back and forth among three or more resistance states of intermediate resistance values to provide a multi-state mode of operation.
The phase-change materials may change states through application of an electrical signal. The electrical signal may be a voltage across or a current through the phase-change material. The signal may be applied from either a voltage source or a current source. The electrical signal may be in the form of one or more electrical pulses. For example, the volume of material may be programmed from its high resistance reset state to its low resistance set state through application of an electrical pulse (e.g. a current pulse) referred to as a set pulse.
While not wishing to be bound by theory, it is believed that the set pulse is sufficient to change at least a portion of the volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state. The volume of material may be programmed back from the low resistance set state to the high resistance reset state by application of an electrical pulse (e.g. a current pulse) referred to as a reset pulse. While not wishing to be bound by theory, it is believed that application of a reset pulse to the volume of material is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state. It is conceivable that other forms of energy, such as optical energy, acoustical energy or thermal energy, may be used to change the state of the volume of material.
A phase-material material may be used to form a phase-change memory element. A phase-change memory array may be arranged as an array of rows and columns of phase-change memory cells. Associated with each of the columns is a bit line and associated with each of the rows is a word line. Each memory cell may comprise a memory element in series with an access device (also referred to as a select device or isolation device). Examples of access devices include diodes, transistors (such a MOS transistors) and threshold switches such as chalcogenide threshold switches or S-type threshold switches (explained in more detail below). Memory elements may be programmed to store different logic states and be interrogated to read the logic state stored therein. They may be used to store program instructions or data for executing a program in, for example, a processing unit.
A memory cell can be selected for a reading operation, for example, by applying suitable select voltages to the word and bit lines corresponding to the selected memory cell and by applying deselect voltages to the word and bits lines corresponding to the deselected element. When current is forced into the selected column, for example, a voltage reached at the selected bit line depends on the resistance of the memory element (which corresponds to logic value stored in the selected memory cell).
For general memory use, either commodity or embedded, the logic value stored in the memory cell may be evaluated by sense amplifiers of the memory. Typically, a sense amplifier includes a comparator receiving the bit line voltage (or a related voltage) and a suitable reference voltage. As an example, if the bit line driven by a read current achieves a voltage that is higher than the reference voltage for having higher resistance than the lower resistance case, the bit may be decreed to correspond to a stored logic value “0”, whereas if the bit line voltage is smaller than the reference voltage for the cell having lower resistance, then the bit may be decreed to correspond to the stored logic value “1”.
Products, such as programmable logic devices, achieve random logic designs by providing standard logic interconnected to user specifications through an X-Y grid. A programmable logic device may include one or more logic gates. A logic gate may perform a logic operation such as, for example, INVERSION, AND, OR, EXCLUSIVE OR, NAND, NOR or EXCLUSIVE NOR. A programmable logic device may include one or more logic blocks. The X-Y grid of a programmable logic device may be conceptually similar to the X-Y grid of a memory array and may include a plurality of X lines (corresponding, for example, to row or word lines) and a plurality of Y lines (corresponding, for example, to column or bit lines). An X line may end at a Y line or a Y line may end at an X line. The X lines may cross (either over or under) the Y lines. The point at which an X line crosses (either over or under) a Y line may be referred to as a cross-over point, a cross-point or a cross-connect.
The X lines may be oriented in a first direction while the Y lines are oriented in a second direction different from the first direction. The X lines may be substantially perpendicular to the Y lines. The X lines may be physically spaced apart from the Y lines. The X lines are preferably insulated from the Y lines, however, it is possible that the X lines may be connected to the Y lines (or even to other X lines) such as through a shorting contact or shorting bar. When interconnecting logic instead of memory elements of a memory array, the X-Y grid may be more random in spacing and more irregular in length than the X-Y grid of the memory array.
In a memory array, the impedance between an X line and a Y line may be very high, like an open circuit, until the select device (also referred to as an isolation device or an access device) is enabled, such as by row selection. Such selection may entail lowering or raising the X line and/or Y line. The select device may be configured such that selecting a particular X line and/or Y line may lower the impedance between a memory element and a corresponding X line or Y line, or between a memory element and a fixed voltage such as ground.
The X-Y grid of conducting lines used for interconnecting logic (such as in a programmable logic array) may have a relatively linear resistance between the lines (instead of a piecewise linear resistance which may exist in a memory array). That is, for a logic device such as a programmable logic array, an OPEN connection between an X line and a Y line may, for example, be represented by a resistance which is relatively high where an open circuit is intended (and may remain open for any combination of voltages on X or Y that are less than the normal operating range (except when programming). Likewise, a CLOSED connection between an X line and a Y line may be represented by a resistance which is relatively low where a short circuit is intended. Or at least a low resistance after a small percentage of the power supply develops across the programmed element. And that low resistance remains whether the two lines are selected or not (unlike a memory where the impedance has to become high when a different memory bit is selected—so that information in the other bit is selected and information in the other bit may be interrogated without being adversely affected by the prior bit selected (thus avoiding a misread or read-disturb during interrogation of the memory bit).
The appropriate programmable connections between the X lines and Y lines (which may be at the cross-points) of programmable logic may be programmed in different ways. One type of programming technology used to selectively determine connections is mask programming. This is done by the semiconductor manufacturer during the chip fabrication process. Examples of mask programmable devices include mask programmable gate arrays, mask programmable logic arrays and mask programmable ROMs. In the case of mask programming, a CLOSED connection may be an actual short circuit, using a contact or via plug between an X line and a Y line at a cross-point, while an OPEN connection may be an actual open circuit where the insulator between the layers is not cleared because a contact or via plug is not present there on the “mask” used to fabricate the chip. This approach is characterized by good layout efficiency and performance, but higher tooling costs and time delay to first article product, since custom masks and layout are used for each different customer product.
In contrast to mask programmable devices, field programmable devices are programmed after they are manufactured. Examples of field programmable devices include programmable ROM (PROM), electrically erasable ROM (EEPROM), field programmable logic arrays (FPLA), the programmable array logic device (PAL®), the complex programmable logic device (CPLD), and the field-programmable gate array (FPGA).
Field programmable devices make use of programmable connections at the cross-points of the X lines and the Y lines that can be programmed after the time of manufacture, and such programming may be done by the manufacturer to customer specification, or by the OEM upon receipt, or by the end customer in the field, and even updated periodically such as through an internet download.
For field programmable devices such as field programmable logic arrays, the programmable connections may be made so that a relatively high resistance between the lines represents an OPEN connection between the lines while a relatively low resistance represents a CLOSED connection between the lines. Products with lower resistance for CLOSED connections may be faster with improved voltage margin, especially if the capacitance of the programmable connection tied to the interconnect lines is low. Programmable connections having a higher resistance for OPEN connections may have lower leakage and better voltage margin (those connections intended to be OPEN connections may have a larger voltage difference across the lines).
The power drained off and heat generated (battery drain in mobile units) by the cross-points intended to be OPEN may be a larger problem in larger logic arrays with more X-Y interconnects, and hence more cross-points. Hence, for non-mask programmed field programmable devices, whether tying together logic or other electronic functions, there is a need for a programmable connection that may provide a relatively low resistance in CLOSED connections and a relatively high resistance in OPEN connections.
A programmable connection for a field programmable device (such as a field programmable logic array-FPLA) may be a volatile or non-volatile connection (the difference being whether the device needs to be re-programmed each time power is restored). For example, when a computer is turned off, the logic pattern desired in the field programmable logic chips may be stored in hard disc. Upon power-on restart, the logic interconnect pattern may be reloaded into the logic device (such as FPLA), at the expense of delayed restart. Such a volatile approach, may store the state of the programmable connection at each cross-point node on a static RAM (SRAM) driving an n-channel cross point transistor, as shown in FIG. 1.
FIG. 1 shows an example of a programmable connection that uses an SRAM to drive the gate of an n-channel transistor at the cross-point of an X line and a Y line. The X line and Y line may be part of a larger X-Y matrix. The p-channel pull-up transistors Q2 and Q4, provide a high logic level near the power supply, and the n-channel pull-down transistors Q6 and Q8, provide a pull-down to the lower power supply, in the usual CMOS fashion. Here, the transistors are also cross coupled into an SRAM so that node N2 or node N4 may be high and the other low. Line PX may select the SRAM through transistor Q12 so that data may be written on line PY (such data may be furnished by a processor on or off-chip). Output node N2 drives the gate of transistor QI (the interconnect transistor), making it conductive when the gate is high or non-conductive when the gate is driven (by programming the SRAM) to a low or off state. The transistor Q10 is coupled between the Y conductive line and the X conductive line.
The programmable connection may be characterized by its worst case capacitance and resistance over the voltage and temperature range of the lines interconnected, a lower resistance when CLOSED providing less delay and better voltage margin. A higher resistance when OPEN provides lower leakage and battery drain, as well as improved voltage margin by reducing line and driver voltage drop from leakage.
In the SRAM type programmable connection example shown in FIG. 1, the source to drain “on” resistance is lower for voltages on the X and Y lines coupled that are less than the power supply to which the gate is driven, since the resistance from source to drain of the n-channel transistor tends to increase when the source or drain voltages approach the gate voltage. Accordingly, in some versions of greater complexity, the n-channel transistor QI may have a special low threshold voltage Vt or may be in parallel with a p-channel transistor with gate driven by node N4. This full mux approach provides lower resistance but at the expense of greater capacitance and increased chip area for each matrix switch.
As a further example, to make such an approach non-volatile, the SRAM in FIG. 1 may be replaced by an EPROM, EEPROM, or Flash transistor properly loaded to drive the n-channel transistor QI, or the SRAM may be mirrored with non-volatile memory such as FeRAM. Programming the non-volatile memory may be accomplished with a special higher voltage or current for the non-volatile element. However, such an approach increases process complexity.
The SRAM or the non-volatile alternative require considerable area in the base silicon to implement the switching element across the X and Y lines. For example, the cross-point transistor alone may take up considerable area that could otherwise be dedicated to logic and interconnect. Further, considerable extra interconnect is necessary to X-Y select the SRAM or its non-volatile equivalent, such as PX and PY wires at each intersection to uniquely select the SRAM cross-point transistor driver or non-volatile programming element as shown in FIG. 1. Extra interconnect similarly may require extra chip area or interconnect layers that may raise cost and complexity of the delivered product.
The programmable connections in field programmable devices such as FPLAs may be formed as non-volatile anti-fuses at the X-Y interconnect. Products using anti-fuses (for example FPLAs from Actel, Inc.), desirably reduce the chip area and layers dedicated to programming the programmable connection, by reducing the semiconductor active devices and interconnect (e.g. PX and PY) at each cross-point.
This approach may also free up base silicon by forming the programmable connection as a thin-film layer between interconnect layers. FIG. 2A shows an anti-fuse 10 coupled between an X line and a Y line. The anti-fuse 10 acts as an OPEN connection before it is programmed. The anti-fuse may be implemented using an insulative breakdown material that is broken down to provide a conductive pathway through application of a sufficiently high voltage across the material. The anti-fuse may be a metal-metal anti-fuse. FIG. 2B shows an example of an anti-fuse 10 that includes a first metal layer 12A, a second metal layer 12B, a dielectric layer 14 and a breakdown layer 16. The metal layers 12A,B may be formed of an alloy of tungsten, titianum and silicon. The breakdown layer 16 may be formed of an amorphous silicon. Once programmed to a lower resistance state, an anti-fuse cannot be readily reversed. Accordingly, testing in the field may be difficult and reversing a programmed anti-fuse may not be possible.
Manufacturers of equipment may find an error in FPLA operation after programming at the factory and shipment to the customer that could be fixed if the programming is reversible, perhaps allowing correction through remote dial-up and download to re-program the logic if the cross-point programming is reversible. Or, the chip may be removed in the field and re-programmed by plugging into an adaptor to a computer.
However, while such an option is possible with SRAM or its non-volatile equivalent, such an option may not be possible with a fuse-based or anti-fuse based approach where reversing the programming is not practical. Instead, the part may be removed and replaced at considerable expense to the manufacturer and inconvenience to the customer.
Further, due to the testing limitations of using irreversible cross-point link anti-fuses to program the interconnect, testing of the arrays intended for use by the customer may be done only indirectly by programming spare but representative anti-fuses before a part is shipped. However, when needed, actual programming of (previously untested) links used by the customer may be unsuccessful, since the links or cross-points actually used may be defective, since they are untested before being shipped or used. Programmable connections found unprogrammable may require return of the unit to the factory or even replacement in the final equipment if personalization is done after assembly and is unsuccessful in attempting to program an (untested) fuse.
Each of these discards may be at successively higher cost and require an undesirable manufacturing and field use flow which is incompatible with a more preferred zero-defect manufacturing and use. To better improve “yield” and reduce defects in the field, the size and complexity of irreversible fuse or anti-fuse based approaches may be limited to relatively small arrays of interconnect compared to the more testable SRAM based approaches.
Further, the non-SRAM based approaches may add processing steps, beyond those of making the logic to be interconnected, that excessively raise cost. Customer preferences for lower cost suggest that such additional processing steps are preferably offset by reduced chip size, processing steps, and/or reduced test cost relative to SRAM, since SRAM may take up more chip area but does not add extra process steps.
Accordingly, there is a need for a programmable matrix array (such as, for example, a field programmable matrix array) using a non-volatile programmable connection that may be reversible in the field.